Course Modules

Module 1: Timing Fundamentals

• Setup time
• Hold time
• Clock definitions
• Timing paths

Module 2: Timing Reports

• report_timing
• report_constraint
• report_clock
• report_analysis_coverage

Module 3: Setup Violation Debugging

• Logic depth analysis
• Net dominated paths
• Congestion effects
• Optimization techniques

Module 4: Hold Violation Debugging

• Short path issues
• Delay insertion techniques
• Buffer fixes

Module 5: MMMC Analysis

• Multi Mode Multi Corner
• Timing scenarios
• Corner analysis

Module 6: Constraints (SDC)

• create_clock
• set_input_delay
• set_output_delay
• set_false_path
• set_multicycle_path

Module 7: Clock Analysis

• Clock skew
• Clock latency
• Clock uncertainty
• Clock gating checks

Module 8: Signal Integrity Effects

• Crosstalk
• Noise impact
• Overshoot and undershoot

Module 9: Signoff Timing

• Final timing closure
• ECO fixes
• Timing signoff methodology