Course Modules

Module 1: VLSI Design Flow

• Frontend vs Backend
• ASIC design flow overview
• RTL to GDSII flow
• Technology nodes

Module 2: Linux for VLSI Engineers

• Basic Linux commands
• File management
• Grep / awk for log analysis
• Shell scripting basics

Module 3: Physical Design Basics

• Standard cells
• Library files (LEF, DEF, LIB, GDS)
• Timing concepts

Module 4: Floorplanning

• Core utilization
• Macro placement
• Power planning
• IO placement
• Congestion analysis

Module 5: Placement

• Global placement
• Detailed placement
• Congestion optimization
• Placement timing optimization

Module 6: Clock Tree Synthesis (CTS)

• Clock tree structure
• Clock skew
• Clock latency
• Useful skew concepts

Module 7: Routing

• Global routing
• Detailed routing
• DRC fixing
• Antenna violations

Module 8: Timing Closure

• Setup and Hold
• fixes
• Buffer insertion
• Gate sizing
• ECO fixes

Module 9: Physical Verification

• DRC
• LVS
• Metal density checks
• Tapeout flow