Physical Design Services
Physical Design Services
MMR SiliconTech provides end-to-end Physical Design implementation services for ASIC and SoC designs from netlist to GDSII with focus on performance, power, and area (PPA).
Our Expertise
- Floorplanning and Power Planning
- Placement and Optimization
- Clock Tree Synthesis (CTS)
- Routing and Route Optimization
- Timing Closure
- Physical
- Verification support
Key Activities
- Macro placement and congestion analysis
- Power grid design and IR drop awareness
- Placement optimization for timing and area
- Clock tree balancing and skew optimization
- Routing congestion mitigation
- Setup and Hold timing closure
Tools
- Synopsys ICC2
- Cadence Innovus
- Synopsys Fusion Compiler
- Deliverables
- Timing clean design
- DRC/LVS ready layout
- GDSII for tapeout